The present invention relates to clock generators generally and, more particularly, to a clock generator configured to receive a series of configuration signals and generate a series of output signals bussed through programmable interconnections.
Conventional approaches to frequency generation include constructing a clock generator that generates a fixed frequency signal. The frequency of the clock generator is determined by using a specific pattern during the manufacturing process involved in the wafer production of the clock generator. An important competitive advantage can be obtained by providing a clock generator that can be configured late in the manufacturing process, preferably after wafer fabrication. Phase-locked-loop (PLL) based clock generators typically use read only memory (ROM) tables to store frequency selection and configuration information. The frequency selection information can be altered by using a device specific mask during wafer fabrication. A disadvantage with this technique is that once the device has been fabricated, the device can no longer be re-configured. The functions of the device pins are also predefined based on the internal logic used to implement the functions.
Another conventional approach used to obtain late configuration for PLL-based clock generators is accomplished by implementing a number of electrically programmable fuses made of aluminum, polysilicon or some other type of metal that is appropriate for fuse fabrication. These fuses control gates and multiplexers providing limited configuration control. These fuses could then be programmed after production of the clock generator. The fuse technique provides somewhat of a competitive advantage by reducing the number of parts required to be stored in inventory at any given time. The late programming of the fuses also reduces the time necessary to produce the clock generator. However, this technique suffers from the disadvantage of having limited configuration information that can be stored. As a result, the implementation of clock generators that generate new frequencies or functions often requires the design and development of a new device. Some conventional approach devices can implement more than one frequency table on a single ROM, but are limited to the specific pre-defined frequencies available in the original ROM mask.
Another conventional approach that could be used to obtain late configuration of clock generators is accomplished by using floating gate storage (e.g., EPROM, EEPROM, Flash, etc.) which can be programmed by storing a charge on a floating transistor gate which forms an electrically programmable ROM to store frequency or configuration information. Also similar to the fuse technique would be the disadvantage of storing only a limited amount of configuration information.
The present invention concerns a circuit and method for implementing a configurable clock generator comprising a logic circuit, a configurable matrix and a phase-locked loop. The logic circuit may be configured to generate a plurality of control signals. The configurable matrix may comprise a plurality of interconnections that may be configured to (i) receive the plurality of control signals from the logic circuit and (ii) bus the control signals to the phase-locked loop. The plurality of control signals may control the operation of the phase-locked loop. In one example, the logic circuit may comprise a sea of gates logic array.
The objects, features and advantages of the present invention include providing a clock generator that may be configured during or after production of the device by providing a matrix of programmable interconnections that are programmed to provide the desired device function. The programmable interconnections may bus (i) the input/control signals presented to the clock generator that may control the functions of the clock generator and/or (ii) the output signals generated by the clock generator. By using the programmable interconnect matrix to configure the clock generator, a single device may be adapted to meet a much broader range of applications than the limited configurability provided by conventional approaches.